引述 :『 CDFG(Control-Data Flow Graph) is essential data structure for high level synthesis and HW/SW partitioning. CDFG tool is to utilize CDFG with VHDL and C. CDFG tool has * VHDL to CDFG generator * CDFG to VHDL or C translator * CDFG viewer * CDFG parser』

引述 :『VPR is a placement and routing tool for array-based FPGAs, and T-VPack is a logic block packing (clustering) program. VPR was written to allow circuits to be placed and routed on a wide variety of FPGAs to facilitate comparisons of different architectures. It takes two input files, a netlist describing the circuit to be placed and routed, and a description of the FPGA architecture. Optionally, one can also input a placement file to VPR if one desires that an existing placement be routed only.』

引述 :『Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. 』

引述 :『This page is dedicated to linking scripting languages such as Perl,Python and Tcl to any freely available EDA tools. Our basic idea is to make friendly interfaces for any existing EDA engines. Check our paper here and a supplement』